1. Field of the Invention
The present invention relates generally to a semiconductor device and, particularly, to a method for fabricating a semiconductor device having a multi-layer interconnection structure.
2. Description of the Related Art
Conventionally, an effort for speeding up of a working speed according to a scaling law has been made by finely miniaturizing a semiconductor device. On the other hand, a multi-layer interconnection structure is used for interconnecting among respective semiconductor devices in a recent high-density semiconductor integrated circuit device but, with regard to such a multi-layer interconnection structure, when the semiconductor device is very finely miniaturized, interconnection patterns in the multi-layer interconnection structure are close to each other and the problem of an interconnection delay caused by a parasitic capacitance among the interconnection patterns occurs.
Consequently, in order to solve the problem of the interconnection delay in the multi-layer interconnection structure, conventionally, a study has been made to use a low dielectric constant film (so-called low-K film) represented by a hydrocarbon-type or fluorocarbon-type organic insulation film instead of a conventionally used SiO2-based insulation film, as an insulation film that composes an interlayer insulation film in the multi-layer interconnection structure, and to use low-resistant copper (Cu) instead of conventionally used Al for interconnection patterns. Although such an organic insulation film generally has a dielectric constant of 2.3–2.5, the value is lower than that of the conventional SiO2 interlayer insulation film by 40–50%.
Since the low dielectric constant film generally has a small density, there remain problems of the adhesive property with the interconnection pattern, humidity resistance, etc. Accordingly, at present, a so-called hybrid structure is frequently used in which the low dielectric constant film and the Cu interconnection pattern are used for a lower layer part of the multi-layer interconnection structure, where an ultra-fine interconnection pattern is formed and the problem of the interconnection delay may be serious, and the conventional SiO2 interlayer insulation film that is excellent in the adhesion properties is used for an upper layer part of the multi-layer interconnection pattern, where the separation between the interconnection patterns is relatively not dense.
Japanese Laid-Open patent Application No. 14-526916 and Japanese Laid-Open patent Application No. 14-520849 discloses conventional techniques against the present invention.